Many modern applications encode data prior to transmission of the data on a network using cyclic error correcting codes such as Reed-Solomon codes. Such codes are capable of providing powerful error correction capability. For example, a Reed-Solomon code of length n and including n−k check symbols may detect any combination of up to t=n−k erroneous symbols and correct any combination of up to └t/2┘ symbols, where └.┘ denotes the floor function.
Reed-Solomon codes are increasingly used in high speed data applications. For example, IEEE802.3 standards for backplanes prescribe the use of Reed-Solomon codes. However, decoding Reed-Solomon codes quickly enough to satisfy the throughput requirements of such high-speed data applications may be challenging. In one approach, multiple Forward Error Correction (FEC) circuits are instantiated as part of a decoder in order to achieve a desired data throughput. While multiple FEC circuits may be implemented at a relatively low cost compared to overall device cost (overall device cost may include a cost for a die of the required size, digital logic and transceivers, and packaging), other considerations may make such a design undesirable. For example, instantiating as many FECs as required in the maximum case may result in the inclusion of too many application specific components in a Field Programmable Gate Array (FPGA).
For many applications where FEC codes, such as Reed-Solomon codes are used, they are designed for “typical” channels. In cases where the channel is known to have a lower error rate than the code is designed for, a partial decoding of the codeword can be performed. For Reed-Solomon codes, this may take the form of the full codeword being encoded and decoding only a subset of error polynomials. Alternatively, the codeword may be only partially encoded.